The present invention relates generally to variable delay circuits that apply variable delay times for inducing delays to leading and/or trailing edges of an input pulse train and more particularly to a variable delay circuit that increases the update rate of the delay time.
Digital circuits in electric instruments process pulse trains that are sometimes not ideal because of variation in the timing of the leading and/or trailing edges of the pulses in the pulse train caused by outside noise, etc. The variations in the timing of the leading and/or trailing edges in the pulse train is referred to as jitter in the electronics industry. Therefore, digital circuits have to be designed to work even if the leading edges and/or trailing edges of the pulses have a certain level of jitter. A jitter tolerance test is used to inspect the prototype circuit by providing a jittered pulse train to the circuit to confirm that it works in the presence of a jittered signal.
For the jitter tolerance test, a jittered test signal (pulse train) is necessary. If this test signal is produced by inducing jitter to a normal pulse train (called a reference pulse train hereinafter) that is normally provided to the digital circuit, an effective jitter tolerance test can be conducted by comparing the jittered test signal with the reference pulse train. To induce jitter to the leading and/or trailing edges, delays are provided to the desired edges of the reference pulse train and then the delays are modified continuously.
Japanese patent publication No. H07-95022 discloses how to delay at least one of the leading and trailing edges of a pulse. FIG. 1 shows a block diagram. A buffer 1 receives an input pulse train and provides non-inverted and inverted outputs to respective first and second delay circuits 2 and 3. The first and second delay circuits 2 and 3 receive first and second delay setup signals that independently set-up the delay times of the first and second delay circuits 2 and 3. An AND circuit 4 receives the output of the first delay circuit 2 and the non-inverted output of the buffer 1 to provide the logical product to the S input of an SR flip-flop 6. An AND circuit 5 receives the output of the second delay circuit 3 and the inverted output of the buffer 1 to provide the logical product to the R input of the SR flip-flop 6. Therefore, the signal to the S input of the SR flip-flop 6 determines the timing of the leading edge of an output pulse train of the SR flip-flop 6, and the signal to the R input does the timing of the trailing edge of the output pulse train.
The Japanese patent publication No. H07-95022 discloses specific examples of the first and second delay circuits 2 and 3. One is an analog delay circuit that compares a ramp waveform and a reference voltage to change the delay time. Another is a digital delay circuit that selectively couples a plurality of delay elements. The analog delay circuit can change the delay time seamlessly but may not provide the delay as a user desires because of noise on the ramp waveform. The digital delay circuit may provide the delay time as set by the user but when the delay time is changed dynamically, the following problem may be encountered. If a small delay time is set up after a large delay time, the input pulse of the large delay time remains in some of the delay lines and the input pulse of the small delay time reaches the output of the delay line earlier than the large delay time input pulse, which changes the order of the input pulses or mixes the former and latter pulses. This means that the invention disclosed in Japanese patent publication No. H07-95022 is not suitable for inducing jitter.
Japanese patent application No. 2003-76026 (corresponding to Japanese patent publication No. 2004-236279 and U.S. Publication No. 2004/0135606) discloses a variable delay circuit that solves the problem of the order changing or mixing of pulses. FIG. 2 shows a block diagram of an example of the variable delay circuit the Japanese patent application No. 2003-76026 discloses. A switch 14 receives and selectively provides a reference input pulse train to two delay paths 16 and 18. Delay times are independently set-up for the delay paths 16 and 18 to provide desired delay times to the leading and trailing edges of the reference pulse train. The delay data of first and second delay circuits 22 and 24 are provided to registers (not shown) and loaded from a delay time setup circuit 44 during the pulse train passing through the second delay path 18. Similarly, the delay data of third and fourth delay circuits 34 and 36 are loaded from the delay time setup circuit 44 during the pulse train passing through the second delay path 16. The delay data for the two delay circuits in the respective first and second delay paths 16 and 18 are changed to modify the delay times of the leading and/or trailing edges of the pulse train independently.
The variable delay circuit the Japanese patent application No. 2003-76026 discloses uses a switch controller 12 to control the toggling of the switch 14. The switch controller 12 receives an enable signal from the delay time setup circuit 44 after the end of the delay data loading to the respective delay circuits in one of the first and second delay paths 16 and 18, and then it makes the switch 14 switch the terminal when a leading edge of an input pulse train comes. This process is for changing the delay path to pass the pulse train at a seam of the pulse trains.
If a leading edge of the input pulse train comes around a rising of the enable signal, the output of the switch controller 12 may be metastable because the enable signal from the delay time setup circuit 44 and the input pulse train are not synchronized. To avoid the metastable status, cascaded D flip flops may be used as a synchronization circuit as disclosed in U.S. Pat. No. 5,764,710, for example. Therefore, if a leading edge of the input pulse train arrives soon after the enable signal arrives, the switch 14 cannot be switched and, in the actual operation, there is a waiting time of some leading edges after the enable signal arrives before the switch 14 toggles.
As described above, the variable delay circuit described in Japanese patent application No. 2003-76026 confirms the status of each delay data loading and leading edge of the input pulse train for purposes of toggling the switch 14. The delay time setup circuit 44 detects the status of the delay data loading for the delay paths to provide the enable signal to the switch controller 12, and then the switch controller 12 confirms the leading edge of the input pulse train from the synchronization circuit. The status confirmation based process makes the process speed slow. In other words, because the CPU and the delay time setup circuit 44 are not synchronized with the pulse train, the CPU proceeds with the process to confirm the status of each circuit step by step, or by handshakes. What is needed is a variable delay circuit that provides faster delay data updates increasing the induced jitter throughput of the variable delay circuit.